Design of Improved Built-In-Self-Test Algorithm (8n) for Single Port Memory
Manoj Vishnoi1, Arun Kumar2, Minakshi Sanadhya3
1Manoj Vishnoi, Department of ECE, SRM University NCR Campus modinagar India.
2Arun Kumar, Department of ECE, SRM University NCR Campus modinagar India.
3Minakshi Sanadhya, Department of ECE, SRM University NCR Campus modinagar India
Manuscript received on November 01, 2012. | Revised Manuscript received on November 02, 2012. | Manuscript published on November 05, 2012. | PP: 281-285 | Volume-2 Issue-5, November 2012. | Retrieval Number: E1067102512/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a modified March (8n) test algorithm to the Built-In Self-Test (BIST) for Single Port Memory. In this algorithm, test patterns are complemented to generate state-transitions that are needed for the detection of frequently occurring as well as newer occurring faults with the shrinking of channel length. The test pattern will be generated for the single port memory. The use of 8n pattern to generate state transition allow to reducing both of time and energy for detection of faults. As a result, the number of test patterns required is very less than of the traditional method, while the extra hardware is negligible.
Keywords: March Algorithm, BIST (Built-In-Self-Test), Channel Length, Faults, Test-Pattern.