Design & Implementation of Low Power 3-bit Flash ADC in 0.18µm CMOS
Pradeep Kumar1, Amit Kolhe2
1Pradeep Kumar, Department of Electronics & Telecommunication, Rungta College of Engineering & Technology, Bhilai, Chattishgarh, India.
2Amit Kolhe, Department of Electronics & Telecommunication, Rungta College of Engineering & Technology, Bhilai, Chattishgarh, India.
Manuscript received on October 05, 2011. | Revised Manuscript received on October 19, 2011. | Manuscript published on November 05, 2011. | PP: 71-74 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0150081511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper describes the design and implementation of a Low Power 3-bit flash Analog to Digital converter (ADC). It includes 7 comparators and one thermometer to binary encoder. It is implemented in 0.18um CMOS Technology. The pre-simulation of ADC is done in T-Spice and post layout simulation is done in Microwind3.1. The response time of the comparator equal to 6.82ns and for Flash ADC as 18.77ns.The Simulated result shows the power consumption in Flash ADC as is 36.273mw .The chip area is for Flash ADC is 1044um2.
Keywords: CMOS, Comparator, Flash ADC, T-Spice.