Implementation of Multilayer AHB Busmatrix for ARM
E. Raja1, K.V. Ramana2
1E. Raja, Pursuing M. Tech (ECE), Pydah College of Engineering & Technology, Visakhapatnam, (A.P.), India.
2K.V. Ramana, Working as Associate Professor & Head, Department of ECE, Pydah College of Engineering & Technology, Visakhapatnam, (A.P.), India.
Manuscript received on October 03, 2011. | Revised Manuscript received on October 14, 2011. | Manuscript published on November 05, 2011. | PP: 27-30 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0139081511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The multi-layer AHB busmatrix (ML-AHB busmatrix) proposed by ARM is a highly efficient on chip bus that allows parallel access paths between multiple masters and slaves in a system. However, the ML-AHB busmatrix of ARM offers only transfer-based fixed-priority and round-robin arbitration schemes. In this paper, we present one way to improve the arbiter implementation of the ML-AHB busmatrix. The proposed arbiter, which is Self-motivated (SM), selects one of the nine possible arbitration schemes based upon the priority-level and the desired transfer length from the masters so that arbitration leads to the maximum performance. Our SM arbitration scheme has the following advantages: 1) It can adjust the processed data unit; 2) it changes the priority policies during runtime; and 3) it is easy to tune the arbitration scheme according to the characteristics of the target application.
Keywords: ML-AHB busmatrix, Self-motivated Arbiter, fixed-priority arbitration, round-robin arbitration.