Design of Area and Speed Efficient Square Root Carry Select Adder Using Fast Adders
Sanjeev. K1, Sivananda Hariprasth2, Saranya. M3, Sandhya. G4
1Sanjeev. K, 3 rd year Department of Electrical Communication Engineering, SNS College of Technology, Coimbatore (Tamil Nadu) India.
2Sivananda Hariprasth. N, 3 rd year, Department of Electrical Communication Engineering, SNS College of Technology, Coimbatore (Tamil Nadu) India.
3Saranya .M, 3 rd year, Department of Electrical Communication Engineering, SNS College of technology, Coimbatore (Tamil Nadu) India.
4Sandhya. G, 3 rd year, Department of Electrical Communication Engineering, SNS College of Technology, Coimbatore (Tamil Nadu) India.
Manuscript received on August 18, 2015. | Revised Manuscript received on August 29, 2015. | Manuscript published on September 05, 2015. | PP: 129-132 | Volume-5 Issue-4, September 2015 . | Retrieval Number: D2717095415 /2015©BEIESP
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©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: Area and speed are the most important design objectives in integrated circuits. As addition is the basic operation of all computer arithmetic, adders are one of the widely used components in digital integrated circuit design. Since propagation of carry is of major concern in designing efficient adders, this paper presents different fast adders and their performance analysis. Among all the adders discussed Square root Carry Select Adder (SQCSA) provides a good compromise between cost and performance. As, Conventional SQCSA is still area consuming due to dual Ripple Carry Adder(RCA)structures, modifications are done at gate level to reduce area. Modified SQCSA is designed using fast adders like Carry Skip Adder (CSA) and Carry Look-Ahead Adder (CLA) to increase the speed of operation.
Keywords: (SQCSA), (CLA), (CSA), Conventional, designed, Carry, Adder, concern, adders, Among, Modified.