A Study and Analysis of High Speed Adders in Power-Constrained Environment
Vivek Kumar1, Vrinda Gupta2, Rohit Maurya3
1Vivekkumar, ECE Department, National Institute of Technology, Kurukshetra, Haryana, India
2Vrinda Gupta, ECE Department, National Institute of Technology, Kurukshetra, Haryana, India
3Rohit Maurya, ECE Department, National Institute of Technology, Kurukshetra, Haryana, India
Manuscript received on July 01, 2012. | Revised Manuscript received on July 04, 2012. | Manuscript published on July 05, 2012. | PP: 281-287 | Volume-2, Issue-3, July 2012. | Retrieval Number: C0820062312 /2012©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: An overview of the performance of 1-bit full adder in different CMOS logic styles and in depth examination of the advantages and limitations of each of them with respect of speed and power dissipation are presented. Ten 1-bit full adder circuit based on these logic styles are chosen for the extensive evaluation. These circuits were redesigned at the transistor-level in tsmc 0.18 µm technology and comparison reported here uses Mentor Graphics ELDO simulations to assess their performance. The hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The work presented in this paper gives a quantitative comparison of the adder cell performance.
Keywords: Full Adder, logic devices, High-speed, Very large-scale integrated (VLSI) circuit.