An Area Efficient Low Power High Speed Pulse Triggered Flip Flop Using Pass Transistor
G.Sai Manoj1, T.Sreevatsav2, V.Vidya Priyanka3, S.V.K.S. Prasad4, P.Rajesh5
1G. Sai Manoj, Department of ECE, Raghu Engineering College, Visakhapatnam, India.
2T. Sreevastav, Department of ECE, Raghu Engineering College, Visakhapatnam, India.
3V. Vidya Priyanka, Department of ECE, Raghu Engineering College, Visakhapatnam, India.
4S.V.K.S Prasad, Department of ECE, Raghu Engineering College, Visakhapatnam, India.
5P.Rajesh, Department of ECE, Raghu Engineering College, Visakhapatnam, India.
Manuscript received on April 18, 2015. | Revised Manuscript received on April 28, 2015. | Manuscript published on March 05, 2015. | PP: 37-40 | Volume-5, Issue-2, May 2015. | Retrieval Number: B2594055215/2015©BEIESP
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©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: The performance of flip-flop is an important element to determine the efficiency of the whole synchronous circuit. This paper presents an efficient explicit pulsed static single edge triggered flip flop with an improved performance and overcomes the drawbacks of the implicit type pulsed flip flops. The proposed flip flop is having a structure of explicit pulse-triggered with a modified true single phase clock latch based on signal feed through scheme. The proposed flip-flop is compared with existing explicit pulsed single edge triggered flip-flops in terms of power, speed and area. Simulation results based on PTM 90nm CMOS technology reveal that the proposed design features the best power, area and delay performance in several FF designs under comparison.
Keywords: Explicit, Edge-Triggered, Feed through, Latch, Synchronous