Design and Study of Enhanced Parallel FIR Filter using Various Adders for 16 Bit Length
D.Ashok Kumar1, P.Samundiswary2
1Mr. D. Ashok kumar, M.Tech. Student, Department of Electronics Engineering, Pondicherry University, Pondicherry, India.
2Dr. P. Samundiswary, Assistant Professor, Department of Electronics Engineering, Pondicherry University, Pondicherry, India.
Manuscript received on May 02, 2014. | Revised Manuscript received on May 03, 2014. | Manuscript published on May 05, 2014. | PP: 207-213 | Volume-4 Issue-2, May 2014. | Retrieval Number: B2256054214/2014©BEIESP
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©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: Now a day’s parallel Finite Impulse Response (FIR) filter plays very important role in the Digital Signal Processing (DSP) based applications. FIR filters are one of the most widely used fundamental filters in the DSP systems. The parallel FIR filters are derived from FIR digital filter. In this paper, design and study of enhanced parallel FIR filter with various adders using the structure of Fast FIR Algorithm (FFA) based FIR filter and symmetric convolution based FIR filter structures considering 2-parallel and 3-parallel filters is done. These entire filter structures are also designed using Ripple Carry Adder (RCA), Carry save Adder (CSA) and Carry Increment Adder (CIA) by replacing the existing adders with the input bit length and coefficient length of 16-bits. Then the performance metrics of the above two structures is done by designing using Verilog HDL. Further, they are simulated and synthesized using Xilinx ISE 13.2 for Vertex family device of speed -12.
Keywords: Parallel FIR filter, FFA, symmetric convolution, Ripple Carry Adder (RCA), Carry Save Adder (CSA), Carry Increment Adder (CIA).