FPGA Implementation of Single Precision Floating Point Multiplier using High Speed Compressors
Sunil Kumar Mishra1, Vishakha Nandanwar2, Eskinder Anteneh Ayele3, S.B. Dhok4
1Sunil Kumar Mishra, Department of Electronics Engineering, Visvesvaraya National Institute of Technology, Nagpur, India.
2Vishakha Nandanwar, Department of Electronics Engineering, Visvesvaraya National Institute of Technology, Nagpur, India.
3Eskinder Anteneh Ayele, Department of Electronics Engineering, Visvesvaraya National Institute of Technology, Nagpur, India.
4Dr. S. B. Dhok, Department of Electronics Engineering, Visvesvaraya National Institute of Technology, Nagpur, India
Manuscript received on May 04, 2014. | Revised Manuscript received on May 03, 2014. | Manuscript published on May 05, 2014. | PP: 18-23 | Volume-4 Issue-2, May 2014. | Retrieval Number: B2180054214/2014©BEIESP
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©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: Floating point multiplier is one of the vital concerns in every digital system. In this paper, the concepts of High speed compressors are used for the implementation of a High speed single precision binary Floating point multiplier by using IEEE 754 standard. Since compressors are special kind of adder which is capable to add more number of bits at a time, the use of these compressors makes the multiplier faster as compared to the conventional multiplier. For Mantissa calculation, a 24×24 bit multiplier has been developed by using these compressors. Owing to these high speed compressors, the proposed multiplier obtains a maximum frequency of 1467.136MHz. It is implemented using Verilog HDL and it is targeted for Xilinx Virtex-5 FPGA.
Keywords: Compressors, Floating point multiplier, Mantissa, IEEE754 standard, Verilog HDL.