Low Power Configuration Logic Block Design using Asynchronous Static
Debarshi Datta1, Partha Mitra2, Avisek Sen3
1Debarshi Datta, Electronics & Communications, Brainware Group of Institutions, Kolkata, India.
2Partha Mitra, Electronics & Communications, Brainware Group of Institutions, Kolkata, India.
3Avisek Sen, Electronics & Communications, Brainware Group of Institutions, Kolkata, India.
Manuscript received on February 07, 2013. | Revised Manuscript received on February 28, 2013. | Manuscript published on March 05, 2013. | PP: 260-263 | Volume-3 Issue-1, March 2013. | Retrieval Number: A1370033113/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power Configuration Logic Block (CLB) for FPGA is highly desirable in VLSI circuit and system. The CLB is the main block of any FPGA architecture. Each CLB block consists of three static LUT’s for implementing NCL logic function. 27 fundamental NCL logic gates are implemented in each LUT. The proposed CLB has 10 inputs and 3 different outputs, each with resettable and inverting variations. There are two operating modes in each CLB, Configuration mode and Operation mode. The NCL FPGA logic element is simulated at the transistor level using 130nm TSMC CMOS process technology.
Keywords: Configuration Logic Block (CLB), Field Programmable Gate Array (FPGA), Look Up Table (LUT), NULL Conventional Logic (NCL).