Design of Ladner-Fischer and Beaumont-Smith Adders using Degenerate Pass Transistor Logic
Adilakshmi Siliveru1, M. Bharathi2
1Adilakshmi Siliveru, Electronics and Communication Engineering, Sree Vidyaniketan Engineering College, Tirupati, india.
2M. Bharathi, Electronics and Communication Engineering, Sree Vidyaniketan Engineering College, Tirupati, India.
Manuscript received on February 04, 2013. | Revised Manuscript received on February 28, 2013. | Manuscript published on March 05, 2013. | PP: 177-181 | Volume-3 Issue-1, March 2013. | Retrieval Number: A1340033113/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we propose Kogge-Stone and BrentKung parallel prefix adders based on degenerate pass transistor logic (PTL). Threshold loss problem are the main drawback in most pass transistor logic family. This threshold loss problem can be minimized by using the complementary control signals. These complementary control signals are obtained by 5-Transistor XOR-XNOR module. By using these complementary outputs we designed parallel prefix adders based on 10-Transistor full adder. Parallel prefix adders are used to speed up the binary addition and these adders are more flexible to perform addition of higher order bits in complex circuits. The transistor level implementation of parallel prefix adders based on degenerate PTL gives better performance compared to CPL and DPL pass transistor logic.
Keywords: Power Dissipation, degenerate, complexity, Threshold loss.