A0475022112

FPGA Implementation on Reversible Floating Point Multiplier
M.Jenath¹, V.Nagarajan^2
1M.Jenath, Department of Electronics and Communication Engineering, Anna university of Technology. Adhiparasakthi Engineering College, Melmaruvathur, Chennai, India.
²*Dr.V.Nagarajan, Department of Electronics and Communication Engineering, Anna university of Technology. Adhiparasakthi Engineering College, Melmaruvathur, Chennai, India.
Manuscript received on February 15, 2012. | Revised Manuscript received on February 20, 2012. | Manuscript published on March 05, 2012. | PP: 438-443 | Volume-2 Issue-1, March 2012. | Retrieval Number: A0475022112 /2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Field programmable gate arrays (FPGA) are increasingly being used in the high performance and scientific computing community to implement floating-point based system. The reversible single precision floating point multiplier (RSPFPM) requires the design of reversible integer multiplier (2424) based on operand decomposition approach. Reversible logic is used to reduce the power dissipation than classical logic and do not loss the information bit which finds application in low power computing, quantum computing, optical computing, and other emerging computing technologies. Among the reversible logic gates, Peres gate is utilized to design the multiplier since it has lower quantum cost. Operands of the multiplier is decomposed into three partitions of 8 bits each using operand decomposition method. Thus the 2424 bit reversible multiplication is performed through nine reversible 8×8 bit multipliers and output is summed to yield an efficient multiplier optimized in terms of quantum cost, delay, and garbage outputs. This proposed work is designed and developed in the VHSIC hardware description language (VHDL) code and simulation is done using Xilinx 9.1simulation tool.

Keywords: Reversible logic gates, reversible logic circuits, reversible multiplier circuits, quantum computing, Nanotechnology based systems.