Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles
Jagannath Samanta1, Mousam Halder2, Bishnu Prasad De3
1Jagannath Samanta, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
2Mousam Halder, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
3Bishnu Prasad De, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
Manuscript received on January 01, 2013. | Revised Manuscript received on January 02, 2013. | Manuscript published on January 05, 2013. | PP: 330-336 | Volume-2, Issue-6, January 2013.
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: A carry look-ahead adder improves speed by reducing the amount of time required to resolve carry bits. It is widely used in any electronic computational devices. In this paper a 4 bit & 8 bit CLA has been implemented using different static and dynamic logic styles such as Standard CMOS, DCVS Pseudo NMOS, PTL & Domino logic style. The performance of the CLA has been measured by comparing the results in terms of propagation delay, power dissipation and their Power Delay Product. The simulation is done with the help of Tanner EDA tool considering the different feature sizes of 150nm, 200nm & 250nm. Result analyses are also carried out for intrinsic and extrinsic load capacitances. This work will helpful for any circuit designer to build any system.
Keywords: Carry Look-Ahead Adder, TSpice, Standard CMOS, DCVS, Pseudo NMOS, PTL and Domino logic.