New Ternary Logic Subtractor using Carbon Nanotube Field-Effect Transistors
Tahere Panahi1, Saideh Naderi2, Tahere Heidari3, Elham Zeidabadi nejad4, Peiman Keshavarzian5
1Tahere Panahi, Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran.
2Saideh Naderi, Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran.
3Tahere Heidari, Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran.
4Elham Zeidabadi nejad, Department of Computer Engineering, Sirjan Branch,Islamic Azad University, sirjan, Iran.
5Peiman Keshavarzian, Department of Computer Engineering, Kerman Branch, Islamic Azad University, Kerman, Iran.
Manuscript received on January 01, 2013. | Revised Manuscript received on January 02, 2013. | Manuscript published on January 05, 2013. | PP: 214-219 | Volume-2, Issue-6, January 2013. | Retrieval Number: F1133112612/2013©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, we present a new Ternary logic Subtractor (TLS) that is implemented by CNTFET. In addition, we investigate the design of two Novel subtractors based on the proposed TLS. Ternary results are better than the Binary ones. Results show large decrements in delay time. Further, the second presented circuit with its Simulation results has demonstrated significant development in speed, area and power consumption. In the past extensive design techniques, Multiple-Valued Logic (MVL) circuits (especially ternary logic inverters) have been proposed by CMOS Technology. Here, the new TLS based on CNTFETs is presented, and wide simulation results have been done by HSPICE.
Keywords: CNTFET, Subtractor, Multiple-Valued Logic.