Floating-Point FPGA: Architecture Performance and Modeling
Shaik Ayesha1, B.V. Ramana2, K.V. Ramana Rao3
1Shaik Ayesha, M. Tech, Department of ECE, Pydah College of Engineering & Technology, India.
2B.V. Ramana, M. Tech, Department of ECE, Pydah College of Engineering & Technology, India.
3K.V. Ramana Rao, Associate Professor & Head, Department of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on October 15, 2011. | Revised Manuscript received on October 26, 2011. | Manuscript published on November 05, 2011. | PP: 402-404 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0253101511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimized for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing data paths; the precise amount of each type of resources can be customized to suit specific application domains. Issues and challenges associated with the design flow and the architecture modeling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. We assume that current proposed architecture can achieve 2.5 times improvement in speed and 18 times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.
Keywords: Architecture, field-programmable gate array (FPGA), Floating Point, Application domains, modeling.