Mac Architecture – Accumulator Based on Booth Encoding Parallel Multiplier
K. Hima Bindu1, K. Bala Souri2, K. V. Ramana Rao3
1K. Hima Bindu, M. Tech, Department of ECE, Pydah College of Engineering & Technology, India.
2K. Bala Souri, M. Tech, Department of ECE, Pydah College of Engineering & Technology, India.
3K.V. Ramana Rao, Associate Professor & Head, Department of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on October 15, 2011. | Revised Manuscript received on October 26, 2011. | Manuscript published on November 05, 2011. | PP: 385-388 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0249101511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The MAC provides high speed multiplication with accumulative addition. In this paper, we study the various parallel MAC architectures and then implement a design of parallel MAC based on some booth encodings such as radix-4 booth encoder and some final adders such as CLA, Kogge stone adder and then compare their performance characteristics. The one most effective way to increase the speed of a multiplier is to reduce the number of the partial products. Although the number of partial products can be reduced with a higher radix booth encoder, but the number of hard multiples that are expensive to generate also increases simultaneously. To increase the speed and performance, many parallel MAC architectures have been proposed. Parallelism in obtaining partial products is the most common technique used in this implemented architecture.
Keywords: Radix-4 Booth multiplier, CLA, multiplier and accumulator (MAC).