Functional Verification of GPIO Core using OVM
L. Veera Raju1, B. Kali Vara Prasad2, A. L. G. N. Aditya3, A. Jhansi Rani4, D. Naga Dilip Kumar5
1L. VeeraRaju, M.tech VLSI, K L University, Vijayawada, India.
2B. KaliVara Prasad, E.C.E Dept, K L University, Vijayawada, India.
3A. L. G. N. Aditya, M.tech VLSI, K L University, Vijayawada, India.
4A. Jhansi Rani, M.tech VLSI, K L University, Vijayawada, India.
5D. NagaDilip Kumar, M.tech VLSI, K L University, Vijayawada, India, 9052290361., (e-mail:dilipnaga@gamil.com)
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 534-537 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0644042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The OPB GPIO design provides a general purpose input/output interface to a 32-bit On-Chip Peripheral Bus (OPB). The GPIO IP core is user-programmable general-purpose I/O controller. That is use is to implement functions that are not implemented with the dedicated controllers in a system and require simple input and/or output software controlled signals. It is one of the important peripheral that is listed on any FPGA board. In this project we are atomizing the operation of the GPIO by writing the code in SYSTEM-VERILOG and simulating it in QUESTA MODELSIM. The main aim of this project is to verify the output by using GPIO pins depending up on the preference the code. We verify the GPIO modules by using OVM [Open verification Methodology]. The functional verification of the RTL design of the GPIO is carried out for the better optimum design.
Keywords: GPIO,OPB,QUESTA MODELSIM, System Verilog, FPGA.