Loading

Design and Implementation of Memory-based Cross – Talk Reducing Algorithm to Eliminate Worst Case Crosstalk in On- Chip VLSI Interconnect
Souvik Singha1, G. K. Mahanti2

1Souvik Singha, Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India.
2G.K.Mahanti, Professor, Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, India.

Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 407-413 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0634042212/2012©BEIESP
Open Access | Ethics and Policies | Cite 
© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Cross- talk induced Delay and power consumption are two of the most important constraints in an on- chip bus design. In same metal the ratio of cross-coupling capacitance between adjacent on-chip wires is quite larger. As a consequence, cross- talk interference becomes a serious problem for VLSI design. On chip bus delay maximized by cross-talk effect when adjacent wires simultaneously switch for opposite signal transition directions. In this paper we propose a memory- based cross-talk reduction technique to minimized the cross-talk for onchip buses based on graph representation. In this approach that represents all the illegal code words canonically generates code words efficiently. As a result, a memory-based cross-talk avoidance CODEC would need to partition large buses into small groups. Our approach is applicable for reducing the cross talk, using a unified implicit formulation. It can actually speed up the bus by exploring cross talk among neighboring wire. By using this approach, we have developed a CODEC based algorithm to minimize the cross- talk or interference in on- chip buses.

Keywords: Crosstalk, Bus Encoding, On-chip bus, Crosstalk Free Algorithm, Delay.