Parallel and Digit-Serial Implementations of Area-Efficient 3-Operand Decimal Adders
Tso-Bing Juang1, Hsin-Hao Peng2, Han-Lung Kuo3
1Tso-Bing Juang is with the Department of Computer Science and Information Engineering, National Pingtung Institute of Commerce, Pingtung 900, Taiwan.
2Hsin-Hao Peng is with the Department of Computer Science and Information Engineering, National Pingtung Institute of Commerce, Pingtung 900, Taiwan.
3Han-Lung Kuo is with the Department of Computer Science and Information Engineering, National Pingtung Institute of Commerce, Pingtung 900, Taiwan.
Manuscript received on October 22, 2013. | Revised Manuscript received on November 03, 2013. | Manuscript published on November 05, 2013. | PP: 177-182 | Volume-3 Issue-5, November 2013. | Retrieval Number: E1965113513
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, parallel and digit-serial implementations of area-efficient 3-operand decimal adders are proposed. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient additions with three operands. Unit gate estimates and synthesis results show that our proposed adders are more area-efficient than those previously proposed decimal adders with three operands under the same delay constraints. Also the power consumptions for our decimal adders are lesser. In addition to parallel implementations, the digit-serial 3-operand adders are easily developed to increase the throughput and the operating frequency due to area efficiency. Our proposed decimal adders could be applied to ease the tremendous computation efforts for decimal computations such as multi-operand decimal additions, decimal multiplications and divisions.
Keywords: Computer arithmetic, Decimal additions, Parallel-prefix adders, VLSI design,