Power Efficient Design of Counter on .12 Micron Technology
Simmy Hirkaney1, Sandip Nemade2, Vikash Gupta3
1Simmy Hirkaney, Student of M.Tech. Final year, Technocrat Institute of Technology, Bhopal, (M.P.), India.
2Sandeep Nimade, Assistant Professor, Department of Electronics and Communication, Technocrat Institute of Technology, Bhopal, (M.P.), India.
3Vikash Gupta, Assistant Professor, Department of Electronics and Communication, Technocrat Institute of Technology, Bhopal, (M.P.), India.
Manuscript received on February 20, 2011. | Revised Manuscript received on February 27, 2011. | Manuscript published on March 05, 2011. | PP: 19-23 | Volume-1 Issue-1, March 2011. | Retrieval Number: A007021111
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance is implemented in layout level which develops the low power consumption chip, using recent CMOS, micron layout tools. This paper compares 2 architectures in terms of the hardware implementation, power consumption and CMOS layout using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of Counter in CMOS VLSI. The Microwind program allows the designer to design and simulate an integrated circuit at physical description level.
Keywords: Microwind, micron Technology, layout, asynchronous counter.